module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
    parameter A = 2'b00;
    parameter B = 2'b01;
    parameter C = 2'b10;
    parameter D = 2'b11;
    
    reg [1:0] state,next_state;
    
    always@(posedge clk)
        if(reset)
            state<=A;
        else
            state<=next_state;
    
    always@(*)
        case(state)
            A:next_state=in[3]?B:A;
            B:next_state=C;
            C:next_state=D;
            D:next_state=in[3]?B:A;
        endcase
    
    assign done = state ==D;

    // New: Datapath to store incoming bytes.
    always@(posedge clk)
        case(state)
            A:out_bytes[23:16]<=in;
            B:out_bytes[15: 8]<=in;
            C:out_bytes[ 7: 0]<=in;
            D:out_bytes[23:16]<=in;
        endcase

endmodule
